In general, recent circuits for receiving high speed serial transmission signals employ a method in which serial data is sampled using multi-phase clock signals in a quantity equal to or greater than the number of symbol bits included in serialized data for each character when the reception data is demodulated. The multi-phase clock signals must be in synchronism with a transmission clock signal to be transmitted in association with the serialized data for each character, and they must have phase differences that are equal intervals associated with the intervals between the symbol bits included in the serialized data for each character.
In order to generate multi-phase clock signals having phase differences at equal intervals, such a reception circuit employs a PLL (phase-locked look) including a voltage-controlled oscillator and a phase comparison circuit or a DLL (delay-locked loop) including a voltage-controlled delay element and a phase comparison circuit.
During actual high speed serial digital transmission, so-called jitters as frequency fluctuations having a short period are generated in the serial transmission data and the transmission clock signal because of fluctuations of the power supply voltage of the transmission circuit and disturbances and so on in a transmission circuit. In a reception circuit for high speed serial digital transmission signals, multi-phase clock signals used for sampling reception data must follow up such frequency fluctuations as jitters. In general, a reception circuit utilizing a DLL is a circuit system that is desirable for generating in multi-phase clock signals in a reception circuit for high speed serial digital transmission signals because it is excellent in following up such frequency fluctuations as jitters in the transmission clock signal.
In a reception circuit utilizing a DLL, phase errors of multi-phase clock signals relative to serial transmission data are determined by phase detection characteristics of the DLL as a whole that are determined by the circuit system and performance of the phase comparison circuit forming a part of the DLL. Therefore, a phase comparison circuit for DLL used in a reception circuit for high-speed serial digital transmission must have a circuit system that provides highly accurate phase detection characteristics.
Normally, a phase comparison circuit compares the phases of two input clock signals that are a reference clock signal and a comparison clock signal and judges whether the phase of the comparison clock signal leads that of the reference clock signal or it is delayed from the same. Further, a phase comparison circuit generally operates to detect a phase difference between input clock signals in a range that is greater than (n−1)π and smaller than (n+1)π (n is a natural number) or in a range that is greater than 2(n−1)π and smaller than 2(n+1)π and generates a control voltage proportionate to the phase difference between the input clock signals to provide a negative feedback to a voltage-controlled delay element, thereby controlling the system. The system is designed such that the control voltage output from the phase compassion circuit is stabilized at a reference value (0V, for example) when the phase difference between the input clock signals equals 2nπ, and the DLL is said to be locked when the system becomes stable at the phase difference 2nπ between the input clock signals.
For example, when serialized data for each character under high-speed serial digital transmission includes N symbol bits, a reception circuit that receives the serial transmission data generates multi-phase clock signals including first to (N+1)-th clock signals. Idealistically, there is a phase difference of 2π between the first clock signal and the (N+1)-th clock signal. Therefore, the number of clock signals having substantially different phases is N, and such clock signals are referred to as N-phase clock signals.
In the reception circuit utilizing a DLL, the phase of the first clock signal and the phase of the (N+1)-th clock signal are compared to control delay times of the multi-phase clock signals such that phase differences between respective adjacent two clock signals included in the multi-phase clock signals are accurately locked at 1/N times the period of the transmission clock signal.
In the case of transmission signals having a wide frequency band, the ranges of changes in the phases of the clock signals generated by the reception circuit must be similarly large. However, since phase differences equal to or greater than 4π can occur between the clock signals to be compared in the case where the phases of the clock signals change in wider ranges, measures must be taken to avoid a problem in that the phase comparison circuit locks phase differences of 2 mπ (m represents integers equal to or greater than 2) that are different from 2π. Such a problem is referred to as false lock.
A reception circuit as shown in FIG. 1 is used to avoid that problem. FIG. 1 is a block diagram showing a conventional reception circuit for receiving high-speed serial transmission data according to a sampling method. In this case, since the number of symbol bits included in serialized data for each character is 8 bits, the reception circuit generates clock signals in eight phases as multi-phase clock signals.
A DLL 100 includes a voltage-controlled delay line 103 which outputs multi-phase clock signals φ0 to φ8 on the basis of a received transmission clock signal, a comparison clock signal generation circuit 106 which generates two types of clock signals φ04 and φ48 for phase comparison on the basis of the multi-phase clock signals φ0 to φ8, a phase comparison circuit 107 which compares the phase of the transmission clock signal and the phases of the multi-phase clock signals on the basis of the clock signals φ04 and φ48, and a filter circuit 109 which receives an output signal of the phase comparison circuit 107.
An output signal of the filter circuit 109 is applied to the voltage-controlled delay line 103 as a delay control voltage to form a control system for negative feedback. A signal delay time of the voltage-controlled delay line 103 is controlled by the delay control voltage. The filter circuit 109 is provided to adjust response characteristics of the DLL and, in general a capacity connected between a signal line and a ground potential (capacitor) is used.
In the DLL 100 shown in FIG. 1, the comparison clock signal generation circuit 106 generates the two types of clock signals φ04 and φ48 for phase comparison such that phase differences between respective adjacent two clock signals included in the multi-phase clock signals are locked at accurately ⅛ times the period of the transmission clock signal, and the phase comparison circuit 107 compares the phase of the transmission clock signal and the phases of the multi-phase clock signals on the basis of these clock signals.
A serial-parallel conversion circuit 110 converts received serial data into parallel data by sampling the serial data using the multi-phase clock signals φ0 to φ7 thus generated and by decoding the sampled serial data thereafter.
FIG. 2 is a diagram showing the phase comparison circuit for a DLL in the reception circuit as shown in FIG. 1. As shown in FIG. 2, the phase comparison circuit 107 includes an NAND circuit 301 which obtains the logical product of the clock signals φ04 and φ48 for phase comparison, an NOR circuit 302 which obtains the logical sum of the clock signals φ04 and φ48, and an output circuit 303 which generates an output signal on the basis of a phase comparison signal UP bar output from the NAND circuit 301 and a phase comparison signal DN output from the NOR circuit 302 and supplies the output signal to an output terminal 108.
FIG. 3 is a diagram showing waveforms of the multi-phase clock signals and clock signals for phase comparison in the reception circuit as shown in FIG. 1 and showing logical expressions used for generating the clock signals for phase comparison. As shown in FIG. 3, the clock signal φ04 for phase comparison is generated on the basis of the clock signals φ0 to φ4 included in the multi-phase clock signals, and the clock signal φ48 for phase comparison is generated on the basis of the clock signals φ4 to φ8 included in the multi-phase clock signals. When both of the clock signal φ04 and the clock signal φ48 are at a high level, the output signal of the NAND circuit 301 is at a low level, which results in an increase in a potential at the output terminal 108. When both of the clock signal 404 and the clock signal φ48 are at the low level, the output signal of the NOR circuit 302 is at the high level, which results in a decrease in the potential at the output terminal 108.
FIG. 4A is a diagram showing waveforms of the clock signals for phase comparison and the phase comparison signals when the phase of the clock signal φ8 included in the multi-phase clock signals is delayed from the state as shown in FIG. 3, and FIG. 4B is a diagram showing waveforms of the clock signals for phase comparison and the phase comparison signals when the phase of the clock signal φ8 included in the multi-phase clock signals leads the state as shown in FIG. 3.
When the phase difference between the clock signal φ0 and the clock signal φ8 included in the multi-phase clock signals is greater than 2π (360°) as shown in FIG. 4A, a capacitor of the filter circuit 109 connected to the output terminal 108 of the phase comparison circuit is charged to perform control such that the signal delay time in the voltage-controlled delay line 103 is decreased to make the phase difference equal to 2π.
On the other hand, when the phase difference between the clock signal φ0 and the clock signal φ8 is smaller than 2π (360°) as shown in FIG. 4B, charges in the capacitor of the filter circuit 109 connected to the output terminal 108 of the phase comparison circuit is discharged to perform control such that the signal delay time in the voltage-controlled delay line 103 is increased to make the phase difference equal to 2π. As a result, phase differences between respective adjacent two clock signals included in the multi-phase clock signals are locked at accurately ⅛ times the period of the transmission clock signal.
As apparent from the above description, the phase comparison circuit 107 used in the conventional reception circuit for high speed serial digital transmission signals as shown in FIGS. 1 to 4B compares the phases of the clock signals φ4 and φ48 for phase comparison generated by the comparison clock signal generation circuit 106 on the basis of the clock signals φ0 and φ8 rather than directly comparing the phases of the clock signals φ0 and φ8 included in the multi-phase clock signals generated on the voltage-controlled delay line 103.
Therefore, a phase error generated in the comparison clock signal generation circuit 106 is superposed on a comparison error that occurs in the phase comparison circuit 107, which has resulted in a problem in that the phase detection characteristics of the DLL as a whole become lower than those obtained by directly comparing the phase of the clock signals φ0 and φ8. Further, since gates of different types, i.e., the NAND circuit 301 and the NOR circuit 302, are used, timing errors occur during the operation of the gates, which has resulted in a problem in that the effect of the timing errors cannot be ignored when the phase difference between the clock signals φ0 and φ8 is close to 2π and the level of the delay control voltage is therefore low.
U.S. Pat. No. 6,157,263 discloses a phase comparison circuit for providing a fast and highly accurate PLL. FIG. 5 is a diagram showing the configuration of the phase comparison circuit for a PLL. As shown in FIG. 5, a phase comparison circuit 500 includes two dynamic D latch circuits 501 and 502, a NOR circuit 503 which supplies data to the D latch circuits 501 and 502, and inverters 504 and 505 which invert output signals of the D latch circuits 501 and 502, respectively. Each of the D latch circuits 501 and 502 has a configuration as shown in FIG. 6.
Referring again to FIG. 5, when a reset signal RS is at a low level, the D latch circuit 501 latches a signal at the low level in synchronism with a reference clock signal φREF, and the D latch circuit 502 latches a signal at the low level in synchronism with a VCO clock signal φVCO output from a VCO (voltage-controlled oscillator). When an output signal UP bar of the D latch circuit 501 and an output signal DN bar of the D latch circuit 502 become the low level, the reset signal RS that is output from the NOR circuit 503 becomes a high level to reset the D latch circuits 501 and 502. The output signal UP bar from the D latch circuit 501 and the output signal DN bar from the D latch circuit 502 are inverted by inversion circuits 504 and 505 respectively to be output as phase comparison signals UP and DN.
FIG. 7 is a waveform diagram showing an operation of the phase comparison circuit as shown in FIG. 5. It shows waveforms of the reset signal RS and the phase comparison signals UP and DN that appear when the phase of the VCO clock signal φVCO shifts from the phase of the reference clock signal φREF by 2π to 4π. As shown in FIG. 7, with this phase comparison circuit, it cannot be distinguished between a first case where a phase difference between the VCO clock signal φVCO and the reference clock signal φREF becomes a first integral multiple of 2π and a second case where the phase difference becomes a second integral multiple of 2π. Although a phase comparison circuit having such detection characteristics effectively works for a PLL for detecting a phase difference between input clock signals in a range greater than zero and smaller than 4π, it cannot be used for a DLL which is required to detect a phase difference in a wider range.